The present invention relates to a test circuit and test method of an integrated semiconductor device. In particular, it relates to an improved test circuit and test method of an integrated semiconductor device for judging whether or not the integrated semiconductor device under test is normal.
In recent years, although advancing semiconductor technology has permitted higher integration and increasing miniaturization of large-capacity memories, testing of these memories with an improved efficiency in a shorter period of time has become a large problem. On the other hand, there have also been manufactured a large number of chips provided with embedded memories, such as a microprocessor and DSP. However, testing of these internal memories has also become a large problem, because it is difficult to test the internal memories by using only external terminals.
To solve the foregoing problems, there has conventionally been proposed a test method whereby a test circuit of an integrated semiconductor device is mounted on a chip so as to perform an automatic test. According to the method proposed, the automatic test is performed each time the power source is turned on. In each use, the result of the automatic test notifies the user whether the chip is normal or not, so that its maintenance and reliability in the market are improved advantageously.
There has also been proposed another automatic test method, which is a kind of compact test technique. The method uses a linear feedback shift register (hereinafter referred to as LFSR) in order to compress sequential outputs from an integrated semiconductor device such as a memory. Briefly, the LFSR comprises: a plurality of registers; a plurality of 2-input exclusive-OR gates placed in the stages previous to the above respective registers; and a feedback information generating means for generating feedback information from the output from the register in the final stage and from the output from the resister in a specified middle stage. Below, a description will be given to the automatic test method using the LFSR.
Initially, sequential sets of data are read from a memory such as a ROM, RAM, or PLA and inputted to a parallel-input LFSR so that the inputted information is compressed by the parallel-input LFSR, thereby obtaining the compressed value (signature) of sequential outputs from the parallel-input LFSR.
Subsequently, the signature obtained using the parallel-input LFSR is compared with expected signature inside the chip so as to judge whether or not the sequential outputs are proper. Alternatively, the obtained signature is scanned out by means of a scan path so that it is compared with the expected signature outside the chip, thereby judging whether or not the sequential outputs are proper and hence judging whether or not the memory under test is normal.
As disclosed in "Design and Test of the 80386" by Patrick P. Gelsinger (IEEE, Design & Test of Compt. vol. 4 no. 3, pp. 42-50 June 1987), e.g., the above method for judging whether or not the data is proper inside the chip can be implemented by inputting to an ALU the obtained signature and the expected signature that has been previously stored and storing the result of the exclusive-OR operation, which was carried out by the ALU, in a diagnostic register. In this case, if there is a match between the obtained signature and the expected signature, i.e., if the memory is normal, a zero is stored in the diagnostic register. If there is no match therebetween, i.e., if the memory is not normal, a value other than zero is stored in the diagnostic register.
However, the foregoing test circuit and test method of an integrated semiconductor device are unsatisfactory in terms of comparing the obtained signature with the expected signature inside the chip and judging whether or not the sequential outputs from a memory or an internal functional block are proper, because the following requirements are placed thereon:
(1) In addition to the parallel-input LFSR, a comparing means for comparing the compressed value of the sequential outputs with the expected signature is needed. PA0 (2) If an ALU is used as the above comparing means, it becomes necessary to provide a storing means for previously storing the expected signature as well as to connect the parallel-input LFSR to the above ALU via a data bus. Consequently, a layout restriction occurs if a compact arrangement is to be obtained. PA0 (3) If the foregoing configuration is adopted, the number of blocks to be controlled, such as the above comparing means and storing means, is increased so that complicated control using a microprogram becomes necessary. PA0 (4) Although the expected signature for the chip to be tested is needed outside the chip, the user who cannot know the expected signature cannot use the test originally provided in the chip. PA0 (5) Even if chips that are functionally identical are to be tested, it becomes necessary to prepare and control their respective expected signature, depending on the types of data written in their internal ROM or RAM, so that the data is compared with the corresponding expected signature.
The test circuit and test method of an integrated semiconductor device are also unsatisfactory in terms of comparing the obtained signature with the expected signature outside the chip and judging whether or not the sequential outputs from the memory are proper, because the following requirements, which render the test circuit and method of an integrated semiconductor device intricate and inflexible, are placed thereon: